The trend of technology in in-car entertainment systems is becoming increasingly complex. A simple audio system that sends audio data over copper cables has become a thing of the past. In order to meet the requirements of multi-channel audio processing and distributed video, complex network processing has become more and more popular. In particular, Media Oriented System Transport (MOST) optical networks associated with digital transmission content protection (DTCP) encryption and decryption methods are being adopted by many high- and mid-range vehicles. This trend and the fact that car audio systems often have to adapt to multiple input sources (amplitude and frequency modulation, CD, DVD drive, cellular phone, navigation system input) with varying sampling frequencies puts pressure on DSP vendors to provide improvements. Performance and processor for increased integration.
2. Universal MOST bus-based car high-end entertainment systemThe MOST bus is specifically designed to meet the requirements of demanding automotive environments. This new fiber-based network is capable of supporting 24.8 Mbps of data, providing the added benefit of reducing weight and reducing electromagnetic interference (EMI) compared to previous copper.
DSP Amplifier=DSP Amplifier
Driver InformaTIon Display=Drive Information Display
Head Unit=head drive mechanism
MOST? BUS =MOST? bus
Rear Video Display= Rear Projection Display
Rear View AcquisiTIon=Back View Browse Collection
Camer=Camera
NavigaTIon System=Navigation System
Figure 1: Typical automotive high-end entertainment system based on MOST bus
The MOST bus is based on a ring topology, allowing data to be shared across multiple transmitters and receivers. The MOST bus master (usually located in the head drive mechanism) facilitates data acquisition, so the network can support multiple hosts with up to 64 hosts on a single network. To ensure data security, the bus master will query each slave on the bus and complete automatic key exchange (AKE) upon power up. If the slave device has a valid bus key, it is allowed to send and receive data on the MOST bus using a predetermined protocol.
The MOST transport protocol consists of data blocks divided into frames. Each frame contains stream data, packet data, and control data. The stream data is synchronized with the MOST clock and constantly wraps around the network. The packet data is asynchronous to the MOST clock and is generated as needed, an example of which is e-mail from a wireless personal digital assistant (PDA) device. The bandwidth allocated between the stream data and the packet data in the frame is variable to meet the requirements of the system for a prescribed time, and its control word contains stream information such as the data type, where the data in the frame is found, and the data size. Control information can be allocated every multiple frames and should be regenerated in the receiving device.
3. Audio processing in a car-based entertainment system based on MOST busDVD Player=DVD Player
HeadUnit=head drive mechanism
Amplifier=Amplifier
NavigaTIon System Announcement=Navigation System Notification
Figure 2: Schematic diagram of a car audio entertainment system based on MOST bus
Figure 2 shows a simple MOST bus-based car audio entertainment system. Audio source content from the DVD player, such as PCM, AC3 & DTS, is transmitted to the head drive mechanism via the SPDIF link. The SPDIF link will operate at the sampling frequency of the audio source (FS_in1), for example 44.1 KHz for CD audio and 48 KHz for DVD video content such as AC3 and DTS. When the encoded audio data is to be transmitted to the network, the transmission content must be encrypted to prevent pirate copying before transmission. The optional encryption mechanism for in-vehicle systems is usually DTCP, which is described below.
ADI's BlackFin processor architecture is well-suited for this capability because of its rich peripherals and optimized instruction set, enabling it to perform microcontroller-like (MCU) operations as well as traditional digital signal processors (DSPs). )work. At the same time, the navigation system notification must also be transmitted to the amplifier via the MOST bus to allow the drive to receive commands while driving. These PCM-based signals are usually based on 12.24 KHz stereo, which we call FS_in2.
The MOST transceiver can send and receive multiple audio sources and re-arrange data into blocks for transmission over the bus (as shown in Figure 2).
Some audio packets may use DTCP encryption (such as FS_in1), which is transmitted over the bus to the amplifier section, usually at the rear of the car (see Figure 3). After the audio source data is transmitted over the MOST bus, the DSP must reconstruct the original packet data and, in the case of DTCP encrypted data, decrypt the data stream into its original form. A side effect of transmission over the MOST bus is the loss of the original sample rate of the source audio. Even with clock reconstruction techniques, the original source sample rate cannot be accurately reconstructed, which can result in audible clicks and loss of sound in the DSP buffer.
Multi channe codec=Multi-channel codec
DTCP Decryption=DTCP decryption
DTCP Encryption=DTCP encryption
SPORT Interface=SPORT I interface
Bitstream Detector=bitstream monitor
Audio Decoder=Audio Decoder
Audio Post- Processing=Audio Post Processing
Pac MOS dat=package MOST data
Unpac MOS dat=Unpack MOST data
SRC=Sampling Rate Converter
Figure 3: Amplifier system processing flow
In order to further increase the complexity of the system, the encryption technology using DTCP has become a necessary condition in the network application, thereby providing security for digital data through the network. DTCP has four layers of copy protection:
CCI: Copy Control Information
AKE : device authentication and key exchange
Content encryption
system update
The copy control information (CCI) is based on content transmitted over the network, and it is determined by the content owner, such as "free copy", "copy prohibited", "no more copy", and "copy once". Before exchanging anything, devices on the network must determine if they are the original content. There are two levels of authentication, full authentication and restricted access authentication. After the key exchange, the content can be transferred over the network. The content is encrypted and decrypted using a predefined basic crypto engine and placed in the protected content package of the MOST transport protocol. The protection package has a header signature to identify the content that has been encrypted.
4. Solutions for next-generation system problemsTo address the growing system fundamentals of network-based in-vehicle entertainment systems, Analog Devices has developed the Sharc ADSP-21365 processor.
Misc. Control Pins=Misc. Control Pin
4 Timers=4 timers
333 MHz SIMD SHARC CORE=333 MHz
SIMD
SHARC kernel
Block = data block
I/O Processor with 25 DMA Channels=With 25 DMAs
Channel
I/O processor
Interrupts=interrupt
Sport = port
8 Channels Sample Rate=8 channel sampling rate
Input Data Port (8)/=Input Data Port (8)/
Signal Routing Unit=Signal Routing Unit
Figure 4: ADSP-21365 SHARC Processor for Automotive Entertainment at Analog Devices
The ADSP-21365 is a 32/40 bit SIMD (Single Instruction Multiple Data) signal processor. It has a built-in 4 Mbit ROM and fully supports all multi-channel decoder standards, such as Dolby Digital decoders, DTS decoders, and pre-processing modules including DPL2x and Neo6. Customer-specific pre-processing modules can be completed in 3 Mbit internal RAM, and customers can use Visual Audio (see Section 5) audio-specific development tools to increase their pre-processing product range while reducing design time.
To solve the problem of running multiple audio sources at different basic sample rates, Analog Devices has integrated the AD1896's independent sample rate converter into the ADSP-21365. It features 8 channels of sample conversion and up to 140 dB of performance, multiple audio sources can be combined with zero memory and millions of instructions per second (MIPS) overhead, and all output post processing can be run at a single sample rate Further reduce the complexity of the data stream.
Other audio-specific peripherals include six serial ports and native support for TDM and I2S, as well as an integrated SPDIF Tx/Rx port for direct connection to digital audio sources.
The ADSP-21365 Sharc DSP also includes a hardware based on the DTCP M6 crypto engine (compatible with DTLA). The peripheral has two dedicated DMA buses to allow high speed data transfer to or from M6 to avoid interference from the kernel and local support for encryption and decryption. The ADSP-21365 supports a simple design link for a full DTCP compatible system. The cryptographic engine includes the ability to support dynamic updates of keys. With built-in timers, users can set key updates and switch to a time period that increases overall network security. Audio processing includes the intensive use of FIR and IIR filters. In recursive operations, quantization errors due to the digital representation of the signal may cause degradation in audio quality. High-end audio processors, such as Analog Devices' SHARC processors, use floating point representation of audio signals to reduce this error.
In high-end audio systems, the quality of the sound is usually measured by how accurately a small or very quiet sound is reproduced. As audio signal amplitudes become smaller and smaller, the ability of fixed-point processors to accurately reproduce such signals is limited, but for floating-point processors, the accuracy of maintaining audio levels is within fixed limits and has 186 dB. Minimum SNR. The SHARC processor has 40 bit floating point precision native support and an 80 bit accumulator to provide the best audio performance of any signal processor on the market.
Amplitude=amplitude
40 bit floating point=40 bit floating point
32 bit fixed point=32 bit fixed point
24 bit fixed point=24 bit fixed point
16 bit fixed point=16 bit fixed point
Figure 5: SNR values ​​for fixed-point and floating-point processors
Another important feature of home theater audio processors is the dynamic range. The dynamic range is defined as the amount of ration that can reproduce the minimum and maximum amplitudes of the audio signal without the underflow or overflow of the audio processor. In addition, floating-point processors far exceed the limitations of fixed-point processors.
Dynamic Range (dB) = dynamic range (dB)
Floating Point=Floating Point
Fixed Point=fixed point
Fixed = fixed point
Dynamic Range for floating point is determined by the size of the exponent
= the dynamic range of the floating point is determined by the size of the index
6 dB × 255 exponent levels=1530 dB
=6 dB × 255 exponential = 1530 dB
Dynamic Range for fixed point is determined by the data word size
= The dynamic range of the fixed point is determined by the size of the data word
Figure 6: Dynamic Range Comparison of Floating Point and Fixed Point Processors
As the complexity of the pre-decoder algorithm and the post-decoder algorithm increases, the number of MIPS or execution cycles required to complete many of the combinations required for a home theater experience is also increasing.
To solve these problems, the most obvious way is to increase the clock frequency of the signal processor. Due to the limitations of the silicon process, this approach has many obstacles to implementation, and it has enabled signal processor vendors to solve this problem by improving the architecture. Some signal processor vendors have adopted the MIMD architecture scheme, which is to execute multiple instructions simultaneously to complete multiple data movements in one clock cycle. This architecture requires more memory and therefore directly impacts the cost of the chip. The SHARC processor architecture uses an innovative approach to the SIMD architecture to implicitly complete the second parallel arithmetic unit using the same instructions, thus making the code so dense that the MIPS requirements required to complete these algorithms can be reduced. In view of this SIMD architecture, the audio signal processor can process stereo signals in parallel without additional processing overhead. The SHARC core is based on a fully interlocked 5th-order code pipeline, which means the programmer can write code at any time without worrying about when the data is valid. The algorithm pipeline is optimized to 1 clock cycle, which means that the calculation results are immediately available for further calculations in the next cycle.
Because the ADSP-21365 Sharc processor provides automotive audio-specific peripherals and a SIM bit based on a 32-bit floating-point core, it brings the audio system to a new level.
5. Customize audio post-processing design with Visual Audio development toolsThe historic challenge for DSP users is software development that makes optimal use of processor clock cycles and efficient use of memory. The long-term laborious approach of manually encoding audio signal processing algorithms in assembly language has become increasingly infeasible. In particular, most of the effort is required to create a standard checklist or I am also a function rather than focusing on adding product value to other products. There is therefore a need for an improved method of developing audio software. To meet this need, Analog Devices has developed a VisualAudio? A graphical environment to help design and develop an audio system that uses the SHARC processor family. VisualAudio provides most of the software modules for audio system development engineers, as well as an intuitive graphical user interface, as shown in Figure 6, to design, develop, debug, and test the audio system.
Figure 7: VisualAudio Graphic Interface Display Example
VisualAudio includes a PC-based graphical user interface (GUI, graphics tools), a DSP core (basic structure), and an extensible library of audio algorithms (audio modules). With Analog Devices' VisualDSP++? Used in conjunction with the Integrated Development and Debug Environment (IDDE), VisualAudio provides existing product code optimized for millions of instructions per second (MIPS) and memory utilization. By simplifying the process of developing complex digital signal processing software, VisualAudio reduces development costs, risk and time. As a result, audio system development engineers can focus on increasing the value of their audio products to differentiate them from other products.
Visual Audio tools allow design engineers to focus on developing custom post-processing modules using intuitive graphical tools that combine with a powerful SHARC architecture and built-in ROM decoder functionality to allow for fast, simplified system development and product configuration.
You can download the Visual Audio Tools 30-Day Trial Software from the home page of the Analog Devices website listed on the main reference website.
in conclusionThe requirements of next-generation audio systems are continually demanding audio processors that increase speed and increase integration. To maintain a competitive position in the market, audio processor vendors must provide high-performance devices to keep their customers' leading audio profiles while providing an easy-to-use development tool to save customers time on the market. ADI has completely solved this problem with the introduction of third-generation 32- and 40-bit floating-point SHARC audio processors that deliver industry-leading performance and integrated memory and peripherals. In addition, Visual Audio development tools simplify audio algorithm development by providing existing product code for many common audio processing modules.
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