[PConline News] German media ComputerBase reports that Rambus's plans show that HBM3 is based on a 7nm process, with a bandwidth of up to 4GT/s and a more complex package architecture.
According to the single-chip 1024bit bit width, the speed can be achieved from 512GB/s to 1TB/s, which is a direct quadrupled over HBM2.
As for DDR5 memory, the design target I/O bandwidth is 6.4Gbps, the total bandwidth is 51.2GB/s, the frequency is 4800~6400MHz, and the number of prefetched bits is 16bit, which is double that of DDR4.
In fact, in September of this year, Rambus claimed to have obtained the first complete DDR5 verification product in the laboratory, and the voltage was only 1.1V.
However, it must be pointed out that at least throughout the year 2018, the shadow of HBM3/DDR5 will not be seen, and it will take 2019 as soon as possible.
Whether Rambus is really scary with PPT or if there are really a few brushes, it's unclear. Only hope that this technology will come out, do not rely on patents everywhere to "bite people", and that Intel was hard on Rambus RDRAM was stashed.
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