Market Trends of LSI Packaging
The world's electronic information equipment market, be summed up by LSI package, as shown, total deliveries increased 1 turn in 2003, followed by increases along by the year 2005 is expected to reach in 2001 1.5 times the size.
From the perspective of package form, surface mounting represented by SOP ( Small Outline Package ) and QFP (Quad Flat Package ) is the mainstream, accounting for an overwhelming proportion. This trend is almost unchanged in 2005 . In terms of growth rate, 2005 is expected to increase by 50% over 2001 .
In contrast, DIP ( dual in-line package ) as a representative pin-insertion package only accounted for 10% of the total in 2002 , but the trend of gradual reduction has continued, and it will shrink to about 6% in 2005 . On the other hand, in a BGA (ball grid array) or CSP (chip scale package) as the representative of area array packages show a greater growth rate after 2002, the year 2005 will be three times the size of 2001, reaching All packages have a occupancy rate of more than 10% .
In addition to above, which could have a significant growth will be in the form of 3D package SiP (System in Package). In 2001 , there was almost no statistical data available, but in 2005 it will be five times the scale of 2001 , accounting for more than 3% of the entire package .
Figure 1Â Changes and forecast of demand for multiple packaging forms
Picture 2Â Changes in LSI packaging
Technology Evolution of LSI Packaging
The thermoelectric performance of system products has been continuously improved, especially the demand for high frequency and high pin count, which has prompted the packaging technology to move from the traditional peripheral pin package to the area array package, that is, the pin insertion type has progressed to the surface mount, and then the SCP ( single Chip packaging ) has progressed to SiP . The advent of new packaging forms does not mean that the past packaging will be replaced and disappeared immediately. For a considerable period of time, the past packaging forms will still occupy the mainstream. Even today, SOP and QFP packaged with peripheral pins still account for the majority. The technical changes of various packaging forms are shown in Figure 2 .
Early DIP package pins are located on both sides of the IC , and are mostly used for devices with a pin count of less than 64 , including various memories and microcontrollers. After the surface mount pins is divided into both sides of the SOP and IC pinout around the IC in the LCC (leaded / leadless chip carrier) and QFP form. SOP is used for devices with less than 64 pins , including TSOP ( thin small outline package ) , TSSOP ( thin micro shrink package ) , SSOP ( micro shrink package ) , SOJ ( small size J -type lead) Feet ) etc. QFP is often used in high-pin-count packages for ASICs , logic ICs, and various low-end devices. The pin count ranges from 36-208 and 212-304 .
In order to cope with the increasing number of IC pins and the trend of lighter, thinner and shorter devices, the BGA package form that connects the chip and the circuit board with solder balls has been developed after the 1990s , and has further developed FPBGA ( fine pitch BGA) , CSP , High-end packaging technologies such as FCP ( Flip Chip Packaging ) , WLP ( Wafer Level Packaging ) , TCP ( Tape and Reel Packaging ) , as well as MCP ( Multi-Chip Packaging ) , SiP, etc. that combine multiple packaging technologies to combine multiple chips together , To meet the high performance, high speed, high integration, high I/O number, environmental protection, power saving and other requirements of CPU , PC chipset, graphics chip, FPGA , ASIC chip .
BGA packaging is suitable for high-pin-count IC products, mainly SoC , graphics chipset, FPGA , wireless communication and other application chips, especially the number of I/Os exceeds 300. The traditional pin-insertion type packaging method can no longer meet the needs, BGA packaging As a result, the market has gradually expanded.
CSP is suitable for low-pin count ICs . The packaged IC area is no more than 1.2 times the size of the bare chip . The advantage of CSP is that it is small and thin, and can provide good heat dissipation. It is mainly used for DRAM , SRAM , Flash and other memory products. In particular , the new device DDR II, which is an extension of SDRAM, is developed with super high speed, small size and high capacity. CSP is the standard packaging form. The traditional TSOP packaging can no longer support its basic structure and must be transformed to CSP .
Three major technology trends
Flip Chip technology is a typical wafer-level package, a chip bumps (Bump) and the substrate (Substrate) in place of the wire bonding connection (wire bonding) technique, for I / O number of the above product in 1000, its advantage lies in its ability Significantly improve the electrical properties and heat dissipation efficiency of the product. Flip Chip is suitable for high-pin count, high-speed, multi-function devices, such as high-performance MCU , MPU , ASIC , RF , high-end DSP , SoC , graphics chipset with communication, Internet access, wireless transmission, digital image processing, and GPS functions. And so on, the application level is very extensive. However, the barriers to entry are high, and only the technological winner can take advantage of the market.
The traditional IC packaging process is to first cut the wafer into bare chips, and then test and seal, but WLP simplifies the above process, directly after packaging and testing on the entire wafer, and then cutting into a single die , There is no need to go through any packaging steps in the middle, which significantly reduces the IC size and greatly reduces the packaging cost. The advantage of WLP is that because there is only a solder ball between the chip and the circuit board, the circuit transmission path can be shortened, and the inductance and capacitance can be reduced. Therefore, it can effectively reduce the current loss and the probability of electromagnetic interference, thereby improving the working efficiency of the circuit. ; Due to the lack of plastic or ceramic packaging sealed on the outside of the IC , the heat loss generated during the operation of the IC chip can be directly dissipated from the back of the chip in the form of heat conduction and heat radiation, which can effectively solve the heat dissipation problem of mobile electronic devices. At present, portable electronic products such as mobile phones, PDAs , notebook computers, digital cameras and MP3 players, etc., all benefit from WLP technology. Applications are mainly concentrated in three areas, namely low I/O count IC ( such as analog, radio frequency, power amplifier, power supply device ) , memory (EEPROM , Flash) and passive components. In addition to the continuous increase of low-pin-count devices, the application of high-speed devices such as memory will also continue to develop in the future.
The current stage of SoC development is facing bottlenecks and challenges. For example , the cost of a 0.13 micron mask is as high as $ 1 million. On the other hand, the narrower the process pitch, the greater the gate leakage current, and the miniaturization will also cause high-speed difficulties. Since the individual components in the SiP package are still independent, it can avoid the difficulties in the manufacturing process after the integration of the analog and digital circuits in the SoC design, reduce the complexity of the circuit design, shorten the design time, and ensure the yield rate. Therefore, when the SoC technology is not yet mature, SiP has good development opportunities and will become the first choice of many system manufacturers.
In the past, SiP technology was still based on the 2D form where multiple bare chips combined into a system were placed on the same substrate plane , while the ways to connect IC to the substrate include wire bonding, flip chip and automatic tape and tape bonding. (Tape Automated Bonding , TAB) and other technologies, this type of package still has the disadvantages of too long circuit transmission path and too large package volume. The previous MCM ( Multi-Chip Module ) package is a case of SiP in the form of a 2D plane . In MCM , multiple ICs are placed on the same substrate plane and then connected to each other by wire bonding. However, in addition to the above shortcomings of a long transmission path and difficulty in shrinking the package volume, this type of packaging also has difficulties in controlling the yield rate. In order to improve the above shortcomings, SiP is gradually developing towards the trend of stacking and packaging chips in 3D . 3D stacked packages are divided into two types. One is to directly stack bare chips and connect them to the substrate before being packaged (chip stacked) , and the other is to stack multiple packaged chips and then combine them together (package stacked ) . The former packaging method can only overlap four layers of bare chips at most, and it is difficult to test. The current 3D form of SiP is still based on the latter package stacked , which not only has the advantage of pre-testing, but also the number of layers that can be stacked. There are also more, and can meet the needs of light, thin and short.
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