This article discusses a widely used and efficient IC testing technique known as NAND Tree. The primary purpose of this method is to verify the connectivity between the chip's I/O pins and its PADs. The approach involves using NAND gates to create a cascading structure, where each NAND gate is connected between a PAD and the output of the previous stage. This configuration allows for the detection of any issues in the pin-to-PAD connections by monitoring the behavior of the final output.
The NAND Tree technique is particularly useful during the manufacturing process, as it helps identify faulty connections that could lead to improper signal transmission. In practice, all the input pins are initially set to a low state, ensuring that the final output of the NAND Tree is also low. Then, each pin is sequentially set to high, and the resulting change in the output is observed. A consistent pattern of alternating high and low outputs indicates that all connections are functioning correctly.
The diagram below illustrates a typical NAND Tree configuration. The I/O Pins are labeled, with triangles representing tri-state buffers. Some of these pins are bidirectional, while others are unidirectional—either input or output only. During the test, output-enabled pins and bidirectional pins in output mode are disabled, leaving only the input function active. These input pins act like nodes in a tree, connected through the NAND gates in sequence.
In the example shown, all the pins (labeled 1, 2, 3, ..., n) start at a low level. As each pin is individually set to high, the output of the NAND Tree changes accordingly. When pin 1 is set high, the output goes high. When pin 2 is set high, the output returns to low, and so on. This alternating pattern continues as more pins are activated, creating a waveform that mirrors a clock signal. This regular switching confirms that the connections between the pins and their corresponding PADs are intact.
However, if there is a break or a fault in the connection, the output will remain constant—either always low or always high. This lack of change indicates a problem with the specific pin or its connection to the PAD. By carefully analyzing the output behavior, engineers can quickly isolate and address any issues in the chip's internal wiring.
Overall, the NAND Tree method provides a reliable and straightforward way to test pin-to-PAD connectivity. Its simplicity and effectiveness make it a popular choice in the semiconductor industry, especially during the early stages of chip development and production.
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