This article explores the NAND Tree-based chip testing technology, which is primarily used to verify the integrity of connections between a chip's I/O pins and its PADs. The method involves connecting NAND gates between the PADs and the output of the upper-stage NAND gates. By observing the pin's signal transitions, it becomes possible to detect any issues in the pin-to-PAD connection.
Today, I’ll be discussing a widely used and straightforward IC testing technique known as the NAND Tree. This approach is commonly applied to check for faults in the electrical connections between the chip’s I/O pins and the PADs. The basic idea is to introduce a series of NAND gates along the signal path. One input of each NAND gate is connected to the PAD, while the other is linked to the output of the preceding NAND gate. This creates a cascading structure that ultimately feeds into the final pin output. By monitoring the signal changes at the pin, we can determine if there are any problems with the connection.
The diagram below illustrates a typical NAND Tree configuration. The label "I/O Pin" represents the input/output pins, while the triangle symbol denotes a tri-state buffer. The figure also shows a bidirectional I/O pin, which includes both a unidirectional output pin and an input pin. During the NAND Tree test, the output functionality of these pins is disabled, and only their input function is activated. These input pins act like a chain of switches, connected through the NAND Tree structure.
In the initial setup, all the pins—labeled (1), (2), (3), ..., (n)—are set to a low voltage level. As a result, the final output of the NAND Tree will also be low. Then, by setting the input of pin (1) to high, while keeping the rest low, the output of the NAND Tree should transition to high. Next, when pin (2) is set to high, the output should go back to low, and then high again when pin (3) is set to high. This pattern continues as each pin is sequentially set to high.
As this process continues, the output of the NAND Tree will follow a predictable pattern of low-high-low-high, matching the clock signal. This indicates that all the connections between the I/O pins and the PADs are functioning properly. However, if a connection is broken or faulty, the output may remain stuck at either a constant high or low level, regardless of the subsequent pin inputs. This anomaly signals a potential issue in the chip's internal wiring or connectivity.
Overall, the NAND Tree technique is a powerful and efficient way to identify pin-to-PAD connection problems during IC testing. It provides a clear and visual method for verifying signal integrity, making it an essential tool in the semiconductor industry.
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