The frequency divider is one of the basic designs used in FPGA design. Although most of the current designs, the integrated phase-locked loop resources of the chip manufacturers, such as Xilinx DLLs, are widely used for clocking. Divided, multiplied, and phase shifted. However, for the basic design with low clock requirements, the frequency division and phase shift of the clock through the language is still very popular. Firstly, this method can save the phase-locked loop resources inside the chip. Furthermore, the logic unit that consumes a small amount can achieve the right The purpose of the clock operation. On the other hand, the clock division of the language design shows the designer's understanding of the design language. Therefore, many recruiting units often require candidates to write a crossover (such as odd crossover) to assess the design level and understanding of candidates. The following describes how to divide the various frequency division coefficients:
First, the even multiple of the frequency division: even multiple frequency division should be a familiar frequency divider, which is completely achievable by counter counting. If N times even frequency division is performed, the counter can be counted by the clock to be divided. When the counter counts from 0 to N/2-1, the output clock is inverted, and a counter is given a reset signal to make the next clock. Count from zero. Take this cycle. This method can achieve any even division.
Second, odd multiples: The odd multiples are often asked on the forum. In fact, there are two ways to achieve odd multiplication:
First of all, it can be realized by the counter. For example, if the frequency is divided by three, the counter is triggered by the rising edge of the clock to be divided. When the counter counts to the adjacent value, it is flipped twice. For example, when the counter counts to 1, the output is output. The clock is flipped and flipped again when counting to 2. That is, the count value is flipped twice in the adjacent 1 and 2. The three-way duty cycle thus achieved is 1/3 or 2/3.
If you want to implement a three-way clock with a 50% duty cycle, you can trigger the count by the falling edge of the clock to be divided, and divide by three in the same way as the rising edge, then the three-way clock and rising edge generated by the falling edge. The generated clock is phase-ORed to obtain a three-way clock with a 50% duty cycle. This method can achieve any odd crossover. The general method is as follows: For N times odd-numbered frequency division with 50% duty cycle, firstly, the rising edge trigger is used to perform modulo N counting, and the counting is selected to a certain value to perform output clock inversion, and then (N- 1) / 2 again flipped to get a duty cycle non-50% odd n-divide clock. In addition, the modulo N count of the falling edge trigger is simultaneously performed, and when the output clock is inverted with the same value as the rising edge trigger output clock, the output clock is inverted, and when (N-1)/2 is passed, the output clock is inverted again to generate An odd-numbered n-divided clock that is not 50% empty. Two non-50% n-divided clocks are ORed to obtain an odd-numbered n-divided clock with a 50% duty cycle.
Alternatively, the odd-numbered n-divided clock is first divided by n/2 (with fractions, ie equal to (n-1)/2+0.5), and then divided by two. An odd multiple of the duty ratio of 50% is obtained. Let's talk about the design method of fractional frequency division.
Third, fractional division: First, let's talk about how to divide n+0.5. This division requires operation on the input clock. Basic design idea: For n+0.5 frequency division, firstly count modulo n. When counting to n-1, the output clock is assigned to '1'. When it returns to count 0, it is assigned to 0. Therefore, it can be It is known that when the count value is n-1, the output clock is 1. Therefore, as long as the count value n-1 is kept for half an input clock cycle, the n+0.5 frequency division clock is realized, so that n-1 is kept at half. One clock cycle is a difficult point. It can be found that since the counter is counted by the rising edge of the clock, the count trigger clock can be inverted when the count is n-1, and the falling edge of the clock becomes a rising edge. That is, when the falling edge of the clock during the count value of n-1 becomes a rising edge, the count value n-1 is maintained for only half a clock cycle, and since the falling edge of the clock flip becomes a rising edge, the count value becomes zero. Therefore, the trigger clock is flipped every time a cycle of n+0.5 divided clocks is generated.
Example: A three-way circuit written in Verilog
method one:
//Rising edge triggered crossover design
Module three(clkin, clkout);
Input clkin; / / define the input port
Output clkout; / / define the output?
Reg [1:0] step1, step;
Always @(posedge clkin)
Begin
Case (step)
2'b00: step<=2'b01;
2'b01: step<=2'b10;
2'b10: step<=2'b00;
Default :step<=2'b00;
Endcase
End
Always @(negedge clkin)
Begin
Case (step1)
2'b00: step1<=2'b01;
2'b01: step1<=2'b10;
2'b10: step1<=2'b00;
Default :step1<=2'b00;
Endcase
End
Assign clkout=~(step[1]|step1[1]);
Endmodule
Method Two:
// If the duty cycle = 50%, the first cycle can output the original clock in the second cycle, and the third cycle output is low. This can achieve three-way.
The output is a three-way duty ratio of 1:1.module three(clk,throut);
Input clk ;
Output throut;
Reg q1,q2,d,throut;
Always @(posedge clk)
If(!d)
Q1=1'b1;
Else
Q1=~q1 ;
Always @(negedge clk)
If(!d)
Q2=1'b1;
Else
Q2=~q2 ;
Always @(q1 or q2)
d=q1&q2 ;
Always @(posedge d)
Throut=~throut;
Endmodule
Write the divide-by-way circuit in Verilog language with a duty cycle of 50%: module div_5 ( clkin, rst, clkout );
Input clkin,rst;
Output clkout;
Reg [2:0] step1, step2;
Always @(posedge clkin )
If(!rst)
Step1<=3'b000;
Else
Begin
Case (step1)
3'b000: step1<=3'b001;
3'b001: step1<=3'b011;
3'b011: step1<=3'b100;
3'b100: step1<=3'b010;
3'b010: step1<=3'b000;
Default: step1<=3'b000;
Endcase
End
Always @(negedge clkin )
If(!rst)
Step2<=3'b000;
Else
Begincase (step2)
3'b000: step2<=3'b001;
3'b001: step2<=3'b011;
3'b011: step2<=3'b100;
3'b100: step2<=3'b010;
3'b010: step2<=3'b000;
Default: step2<=3'b000;
Endcase
End
Assign clkout=step1[0]|step2[0];
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