The DVI (Digital Video Interface) was introduced in 1999 by the Digital Display Working Group to use the minimum transformed differential signal (TMDS) as the basic electrical signaling method. The image source generates red, green, and blue signals along with control signals, which are encoded and serialized by the DVI transmitter using a clock signal. These signals are then transmitted through the TMDS channel to the DVI receiver, where they undergo serial/parallel conversion, alignment, decoding, and other processing before being sent to the display device, as shown in Figure 1.
DVI transmits digital signals directly, eliminating the need for analog-to-digital conversion, thus saving time and improving efficiency. It is fully compatible with HDMI in terms of electrical characteristics, making system upgrades more straightforward. The DVI link structure is illustrated in Figure 1.
When receiving DVI signals over long distances, traditional methods involve using a receiving chip combined with an FPGA. However, this approach can increase power consumption and cost. To address this, a design that fully utilizes the built-in resources of an FPGA is proposed. This method uses an FPGA with an integrated TMDS I/O interface, eliminating the need for external chips. The programmable nature of the FPGA allows users to implement designs quickly, reducing the overall development cycle.
DVI’s single TMDS link supports 24-bit color depth. When higher color depths are required and both the graphics card and display support dual-link TMDS, the system activates two TMDS links. Link 0 transmits the first 24 bits of data, while link 1 handles the remaining information. For resolutions and refresh rates exceeding the capacity of a single TMDS link (with a maximum pixel frequency of 165 MHz), the system splits the pixel data between the two links. Odd pixels are sent via link 0, and even pixels via link 1. Since the TMDS links share a common clock, the clock frequency in dual-link mode is halved compared to single-link operation.
The DVI encoder employs TMDS encoding, converting 8-bit pixel data into 10-bit format and 2-bit control signals into 10-bit format as well. The least significant bit is transmitted first. This encoding method highlights two key advantages of TMDS: minimal transformation and DC balancing.
**1 Receiver Design**
**1.1 System Architecture**
The DVI receiver system includes level conversion, clock recovery, phase adjustment, serial/parallel conversion, word alignment, channel alignment, and decoding. The serial signal from the TMDS channel is eventually converted into three 8-bit pixel channels and two 2-bit control signals, as shown in Figure 2.
**1.2 Clock Recovery and Phase Adjustment**
Clock and synchronization are critical in DVI receiver design. The pixel clock from the DVI signal serves as a reference, and the serial data on the TMDS channel runs at 10 times this rate. These clock signals are generated using a PLL circuit, and DDR sampling is used to achieve twice the data rate, requiring only a 5x multiplication of the reference clock.
After long-distance transmission, the data and clock may suffer from large phase offsets, affecting correct sampling. A state machine dynamically adjusts the delay of the serial data using the IODELAY module in the FPGA IO interface. Compared to the DCM module, IODELAY lacks some outputs but can still simulate their functionality. Psdone indicates the completion of the first adjustment, while DO[0] signals overflow when the adjustment exceeds 63 levels.
The video data is random, but four control words are transmitted periodically, allowing the system to detect the relative position of the clock and data. If one of these control words is received, the data is considered valid. The jitter region between sampling windows represents uncertainty in arrival time, and the effective sampling window must be centered for accurate data capture.
**Phase Adjustment Algorithm:**
(1) If the initial clock position is at S2, adjust the IODELAY phase offset to T1 and record it, then to T2 and record again. The midpoint (T2-T1)/2 is the optimal sampling moment.
(2) If the initial position is at S1, move to S2 and repeat the process, adjusting to T1 and T2, then calculate the midpoint.
IODELAY offers faster adjustment during data movement, unlike DCM, which operates on clocks. While IODELAY saves FPGA resources, it requires a 200 MHz working clock, and its phase adjustment steps and amplitudes are fixed, limiting its effectiveness for lower-frequency DVI signals.
**1.3 Serial/Parallel Conversion**
Serial/parallel conversion is achieved using ISERDES in the FPGA IO interface module, avoiding timing issues and saving resources. For 1:10 conversion, two ISERDES units are connected, with one acting as the main unit and the other as the slave. The output of the main ISERDES is connected to the input of the slave, as shown in Figure 4.
Word alignment is also performed after conversion. While ISERDES has a BITSLIP feature, it is slower, so multiple selectors are used instead. The core idea is to detect the control word from the 10-bit rawword and combine it into 20 bits, then sequentially compare the segments until a match is found, allowing the correct byte order to be selected via a multiplexer.
**1.4 Channel Alignment**
Each channel receives a signal from the phase adjustment state machine indicating whether word alignment is valid. When all three channels are valid, the FIFO buffer starts transmitting data, writing and reading continuously. The FIFO is a 16-byte distributed RAM resource. When a control word is detected, the read data stream is delayed until the other channels also detect the control word, ensuring synchronized data output.
**1.5 DVI Decoding**
After channel alignment, the 8-bit pixel data and 2-bit control signals are decoded according to the DVI specification. When DE=0 (blanking period), the 2-bit control signal is processed, and when DE=1, the 8-bit pixel data is decoded.
**2 Simulation Results**
The design was simulated using ModelSim 6.5, with function simulation results shown in Figure 6. Using the H264E_VDATA file as the YUV source, R, G, B signals were generated. At the receiver end, the input consists of TMDS differential signals (blue_p, blue_n, green_p, green_n, red_p, red_n) and the clock (tmdsclk_p, tmdsclk_n). The output includes three 8-bit R, G, B signals, a recovered clock (pixel_clk), and control signals (hsync, vsync, de).
The design was validated on a Xilinx Virtex-5-330T FPGA. Resource utilization is listed in Table 1. Due to the PLL's maximum output frequency of 450 MHz, the main clock runs at 90 MHz, resulting in a theoretical TMDS input data rate of 900 Mb/s.
In actual testing, a DVI signal from a PC graphics card was used over a 1-meter cable with a resolution of 1280×720 and a pixel frequency of 74.5 MHz. After decoding, the FPGA output clear, noise-free dynamic video, confirming the feasibility of the design.
This paper presents an FPGA-based DVI receiver design that conforms to the DVI 1.0 specification. It demonstrates how FPGA-based DVI decoding can reduce resource usage, enhance integration, and make full use of FPGA capabilities.
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