High Cloud Semiconductor launches universal LVDS gearbox interface solution

**Foshan, Guangdong – August 22, 2017** Today, Guangdong Gaoyun Semiconductor Technology Co., Ltd. (referred to as "Gaoyun Semiconductor") announced the release of the GW1N series, which supports both the non-volatile Bee® family and the medium-density Chenxi® family. This series introduces a range of general-purpose LVDS gearbox interface IP cores (Gowin Generic LVDS Gearbox IP) for FPGA chips, including related soft cores, reference designs, development boards, and other comprehensive solutions. The Gowin Universal LVDS gearbox interface IP enables the conversion of clock frequencies and data bit widths between internal logic and external interfaces while maintaining consistent data throughput. It supports both sending and receiving functions, with all Gowin FPGA chips capable of handling gearbox switching ratios of 1:1, 1:2, 1:4, 1:7, 1:8, and 1:10. Additionally, GW1N-6/9 devices also support a 1:16 switching ratio. To meet different requirements for the phase relationship between clock and data signals, Gowin's solution offers both edge-aligned and center-aligned options. Gowin’s FPGA chips feature dedicated modules designed to construct high-speed LVDS interfaces. These modules are tailored to meet specific customer needs regarding bandwidth, alignment, transceiver capabilities, and switching ratios, working collaboratively to deliver the desired functionality. Key features include: - **High-Speed Low-Skew Clock (HCLK):** Supports high-performance data transmission via I/O. - **Internal System Clock (GCLK):** Must utilize the global clock network. - **High-Speed Clock Divider Module:** Generates phase-matched divided clocks from the input HCLK. - **Phase-Locked Loop Module:** Achieves clock frequency multiplication, division, and phase shifting. - **Serial-to-Parallel Receiving Side Module:** Implements the gearbox function. - **Parallel-to-Serial Transmission Side Module:** Also implements the gearbox function. - **Delay Modules per I/O:** Provide approximately 3200ps of total delay through 128 steps. "Gowin’s Universal LVDS gearbox interface IP fully leverages various embedded dedicated modules within Gowin’s FPGA chips, enabling LVDS I/O interface speeds to reach up to 800Mbps to 1.2Gbps," explained Mr. Xu Cai, Product Application Manager at Gaoyun Semiconductor. "In the TCON market application, LCD screen timing is controlled by FPGA, converting input video signals like LVDS into formats suitable for data driver circuits, such as Mini-LVDS or RSDS signals, and delivering them to the appropriate driver circuits in real-time. The Gowin FPGA chip perfectly aligns with the TCON market demand in terms of LVDS differential pin count and interface performance." "The rapid advancement of video capture and display technologies has led to widespread adoption of various high-speed LVDS-based interfaces, such as Mini-LVDS, MIPI CSI-2/DSI, in mobile phones, tablets, VR, in-car entertainment systems, human-machine interfaces (HMI), and more," stated Mr. Huang Jun, Vice President of Marketing and China Sales Director at Gaoyun Semiconductor. "This growing demand for video interface bridging and image processing solutions has prompted Gaoyun Semiconductor to develop a universal LVDS gearbox interface solution. By combining the advantages of our FPGA chips—non-volatility, compact packaging, and embedded large-capacity SDRAM—we can offer video interface bridging and image processing solutions to consumers, automotive electronics, and industrial display markets, helping users accelerate their time-to-market." --- **Key Features of the IP** The LVDS I/O data rate currently supports up to 1.2Gbps, while the internal fabric clock operates at 120MHz for the GW1N series and 200MHz for the GW2A series. **TCON System Architecture and IP Call** Video image data is first converted into parallel video signals via the LVDS 7:1 receiving module. Then, an image processing module transforms these signals into the format required by the LCD screen before transmitting them using the mini-LVDS 4:1 sending module to the LCD panel.  *GW1N/1NR, GW2A/2AR Series FPGA Chips* The GW1N/1NR and GW2A/2AR series FPGA chips support multiple differential level standards such as LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVPECLE, and RSDSE. Their I/O logic internally integrates a variety of transmission ratio gearboxes. **Development Boards and Reference Designs** Gaoyun’s general-purpose LVDS gearbox interface IP, reference designs, and development boards currently support the GW1N-4K FQFP144 packaged FPGA chip for connecting to LVDS receive signals and mini-LVDS transmit signals. Future upgrades will extend support to the GW2A series, further enhancing LVDS I/O interface performance.  **About Gaoyun Semiconductor** Established in January 2014, Guangdong Gaoyun Semiconductor Technology Co., Ltd. is dedicated to developing domestic FPGA solutions and advancing their industrialization. The company aims to launch national-brand FPGA chips with core independent intellectual property rights. Its mission is to provide customers with the highest-quality services, offering one-stop solutions that include chips, design software, soft cores, reference designs, and demo boards. For more information, visit: [http://www.gaoyunsemi.com](http://www.gaoyunsemi.com). --- This announcement marks another milestone in Gaoyun Semiconductor's commitment to innovation and technological advancement in the semiconductor industry.

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