High Cloud Semiconductor launches universal LVDS gearbox interface solution

    **Foshan, Guangdong, August 22, 2017** – Guangdong Gaoyun Semiconductor Technology Co., Ltd. (referred to hereafter as "Gaoyun Semiconductor") today announced the launch of its GW1N series, which includes both the non-volatile Xiao Bee® family and the medium-density Chenxi® family. This series introduces a comprehensive set of general-purpose LVDS gearbox interface IP cores (Gowin Generic LVDS Gearbox IP) for FPGA chips. These cores are designed to support essential functionalities like data transmission and clock frequency conversion, ensuring seamless data throughput. Alongside these cores, the announcement also highlights the availability of related soft cores, reference designs, development boards, and other complete solutions. The Gowin Universal LVDS gearbox interface IP facilitates the dynamic switching of clock frequencies and data bit widths between internal logic and external interfaces while maintaining consistent data throughput. It supports both sending and receiving functions, with all Gowin FPGA chips offering gearbox switching ratios of 1:1, 1:2, 1:4, 1:7, 1:8, and 1:10. Additionally, GW1N-6/9 devices feature an extended switching ratio of 1:16. Addressing specific customer requirements for the phase relationship between clock and data paths, this solution offers both edge alignment and middle alignment options. Gaoyun’s FPGA chips come equipped with dedicated unit modules tailored for constructing high-speed LVDS interfaces. These modules are integrated and functionally coordinated based on specific customer needs regarding bandwidth, alignment, transceiver capabilities, and switching ratios. Key features include: - **High-Speed Low-Skew Clock (HCLK):** Ensures efficient data transmission. - **Internal System Clock (GCLK):** Essential for synchronization within the system. - **High-Speed Clock Divider Module:** Generates synchronized divided clocks. - **Phase-Locked Loop Module:** Facilitates clock frequency multiplication, division, and phase shifting. - **Serial-to-Parallel Receiving Side Module:** Implements the gearbox functionality. - **Parallel-to-Serial Transmission Side Module:** Also implements gearbox functionality. - **Delay Modules per I/O Pin:** Provide approximately 3200ps of total delay. As Mr. Xu Cai, the Product Application Manager at Gaoyun, explained, "Gowin's Universal LVDS gearbox interface IP leverages the embedded unit modules within our FPGA chips, enabling speeds of up to 800 Mbps to 1.2 Gbps. In the TCON market, where LCD screens require precise timing control, our FPGA chips efficiently convert input video signals like LVDS into formats suitable for data drivers, such as Mini-LVDS or RSDS, ensuring timely activation of the data driving circuits." The rapid evolution of video capture and display technologies has led to widespread adoption of high-speed LVDS-based interfaces like Mini-LVDS and MIPI CSI-2/DSI in applications such as smartphones, tablets, VR, and automotive infotainment systems. Mr. Huang Jun, Vice President of Marketing and Sales Director of China at Gaoyun Semiconductor, noted, "With our new universal LVDS gearbox interface solution, we aim to provide flexible, efficient solutions to bridge video interfaces and perform image processing for consumer, automotive, and industrial display markets. Our FPGA chips, with their non-volatile properties, compact packaging, and embedded SDRAM, empower users to accelerate their time-to-market." **Key Features of the IP Core:** - **Operating Frequency:** The LVDS I/O data rate reaches up to 1.2 Gbps, with internal fabric clock rates of 120 MHz for the GW1N series and 200 MHz for the GW2A series. **TCON System Architecture and IP Call:** The video image data is first converted into parallel video signals via the LVDS 7:1 receiving module, processed into the required LCD format, and then transmitted to the LCD screen using the mini-LVDS 4:1 sending module. Gaoyun’s GW1N/1NR and GW2A/2AR series FPGA chips support multiple differential level standards, including LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVPECLE, and RSDSE, with built-in gearbox transmission ratios. **Development Boards and Reference Designs:** Gaoyun’s general-purpose LVDS gearbox interface IP, along with reference designs and development boards, currently supports the GW1N-4K FQPF144 packaged FPGA chip for receiving LVDS signals and sending mini-LVDS signals. Future upgrades will extend support to the GW2A series, enhancing LVDS I/O interface performance. **About Gaoyun Semiconductor:** Established in January 2014, Guangdong Gaoyun Semiconductor Technology Co., Ltd. focuses on developing domestic FPGA solutions and promoting their industrialization. The company strives to deliver FPGA chips with core independent intellectual property rights under a national brand. Gaoyun aims to offer users the highest quality service, providing a one-stop-shop for chips, design software, soft cores, reference designs, and demo boards. For more information, visit [Gaoyun Semiconductor's website](http://www.gaoyun-semi.com). --- This newly developed solution not only meets current market demands but also positions Gaoyun Semiconductor as a leader in providing cutting-edge FPGA technology for diverse industries.

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